module mux4to1(in1,in2,in3,in4,s1,s2,out);

input [7:0] in1,in2,in3,in4;

input s1, s2;
output [7:0] out;

reg [7:0] out;

initial begin
out[7:0] = 8'b00000000;
end

always @(*)
begin
 case({s2,s1})
  2'b00 : out = in1;
  2'b01 : out = in2;
  2'b10 : out = in3;
  2'b11 : out = in4;
  endcase
  end
  endmodule
  
